Post Doctorate Research Associate - Hardware Design Methodologies
Employer: Pacific Northwest National Laboratory · Location: Richland, Washington · Posting: PNL-12052 · Type: TEMPORARY · Pay: $69,000-$119,100/yr
Duties
Overview At PNNL, our core capabilities are divided among major departments that we refer to as Directorates within the Lab, focused on a specific area of scientific research or other function, with its own leadership team and dedicated budget. Our Science & Technology directorates include National Security, Integrated Discovery Sciences, and Energy and Environment. In addition, we have an Environmental Molecular Sciences Laboratory, a Department of Energy, Office of Science user facility housed on the PNNL campus. The Integrated Discovery Sciences Directorate (IDSD) leads fundamental research across biology, chemistry, earth and environmental sciences, materials science, advanced computing, artificial intelligence, quantum information science, mathematics, autonomy, and DOE national user facilities. Our vision is to accelerate scientific discovery by observing, understanding, simulating, predicting, and controlling dynamic biotic-abiotic processes and interactions within complex biological, chemical, material, and Earth systems. We intentionally connect disciplines to advance fundamental discovery science, develop transformative scientific capabilities, and address the nation's most important challenges in energy, environmental resilience, biotechnology, advanced manufacturing, health, and national security. Responsibilities The Pacific Northwest National Laboratory (PNNL) Future Computing Technology Group is seeking exceptional Post-Doctoral Research Associates to advance research in next-generation electronic design automation (EDA), specialized computing systems, and hardware prototyping. As the complexity of computing systems continues to increase, new methodologies are required to dramatically improve the productivity, automation, and accessibility of hardware design. Our team is developing innovative approaches that span the entire hardware design lifecycle, from high-level programming models and compiler technologies to high-level synthesis (HLS), architecture exploration, register-transfer level (RTL) generation, physical implementation, prototyping, and experimental validation. This position offers a unique opportunity to work at the intersection of compilers, high-level synthesis, computer architecture, artificial intelligence (AI) for hardware design, and semiconductor prototyping. The successful candidate will contribute to research on advanced HLS capabilities, compiler-driven hardware generation, automated design-space exploration, and methodologies for translating high-level application descriptions into efficient hardware implementations. Research may span open-source and commercial design ecosystems and include field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) targets, heterogeneous and domain-specific accelerators, chiplet-based systems, and emerging computing architectures. A major objective is to develop scalable, reproducible, and increasingly automated methodologies capable of moving from application and architectural specifications through hardware implementation, prototyping, and eventual silicon realization. As a member of our collaborative and multidisciplinary team, the successful candidate will work with researchers in computer architecture, compilers, EDA, AI, semiconductor technologies, and scientific application domains. The position provides access to advanced computational resources, semiconductor design tools, prototyping platforms, electronics laboratory facilities and opportunities to participate in hardware fabrication and experimental validation activities. It also provides substantial opportunities to publish at premier conferences and journals and contribute to open-source research software. Responsibilities : Develop novel and scalable methodologies for electronic design automation, high-level synthesis, and hardware/software co-design. Develop compiler and intermediate-representation technologies for translating high-level applications and computational models into optimized hardware implementations. Investigate AI-assisted and autonomous hardware design methodologies, including automated design-space exploration, optimization, verification, and iterative refinement. Design and evaluate specialized computing architectures and accelerators for scientific computing, artificial intelligence, and other emerging workloads. Develop and extend research infrastructure spanning compiler technologies, high-level synthesis, RTL generation, simulation, synthesis, verification, and physical implementation. Develop and evaluate methodologies for transitioning hardware designs from high-level specifications through FPGA prototyping and ASIC implementation. Participate in ASIC design and tapeout activities, including design integration, verification, synthesis, physical design, and preparation for fabrication. Contribute to experimental validation of prototype and fabricated hardware and to methodologies that correlate measured hardware behavior with compiler, architectural, and design predictions. Collaborate with researchers across computer science, electrical engineering, semiconductor technology, and scientific application domains. Develop high-quality research software and, where appropriate, contribute results to open-source software ecosystems. Publish research findings in leading peer-reviewed conferences and journals and present results to the broader research community. Qualifications Minimum Qualifications: Candidates must have received a PhD within the past five years (60 months) or within the next 8 months from an accredited college or university. Preferred Qualifications: PhD in computer engineering or electrical engineering. Electronic design automation (EDA) and hardware synthesis methodologies. High-level synthesis (HLS) and hardware/software co-design. Compiler infrastructures and intermediate representations, particularly the LLVM and MLIR compiler infrastructures Hardware description languages such as Verilog, SystemVerilog, or VHDL. RTL simulation, synthesis, verification, and performance analysis. Field-programmable gate array (FPGA) design and prototyping. Application-specific integrated circuit (ASIC) design flows and semiconductor tapeout. Physical design and layout tools using open-source and/or commercial EDA toolchains. Hands-on experience working with electronics in a laboratory environment, including hardware prototyping, test and measurement equipment, system bring-up, or hardware debugging. Open-source EDA technologies such as Yosys, Verilator, OpenROAD, or related tools. Commercial FPGA or ASIC design environments. Design-space exploration and optimization techniques. Artificial intelligence and machine learning (AI/ML) techniques applied to compilers, architecture, or electronic design automation. Computer architecture, domain-specific accelerators, heterogeneous computing, or chiplet-based systems. Experience working with semiconductor process design kits (PDKs), standard-cell libraries, or hardware intellectual property (IP). Development of substantial research software using languages such as C++, Python, or related systems-programming languages. Experience with collaborative software development, version control, automated testing, and reproducible research workflows. Hazardous Working Conditions/Environment Not applicable. Testing Designated Position This is not a Testing Designated Position (TDP). About PNNL Pacific Northwest National Laboratory (PNNL) is a world-class research institution powered by a highly educated, diverse workforce committed to the values of Integrity, Creativity, Collaboration, Impact, and Courage. Every year, scores of dynamic, driven people come to PNNL to work with renowned researchers on meaningful science, innovations and outcomes for the U.S. Department of Energy and other sponsors; here is your chance to be one of them! At PNNL, you will find an exciting research environment and excellent benefits including health insurance, and flexible work schedules. PNNL is located in eastern Washington State—the dry side of Washington known for its stellar outdoor recreation and affordable cost of living. The Lab’s campus is only a 45-minute flight (or ~3 hour drive) from Seattle or Portland, and is serviced by the convenient PSC airport, connected to 8 major hubs. Commitment to Excellence and Equal Employment Opportunity Our laboratory is committed to fostering a work environment where all individuals are treated with fairness and respect while solving critical challenges in fundamental sciences, national security, and energy resiliency. We are an Equal Employment Opportunity employer. Pacific Northwest National Laboratory (PNNL) is an Equal Opportunity Employer. PNNL considers all applicants for employment without regard to race, religion, color, sex, national origin, age, disability, genetic information (including family medical history), protected veteran status, and any other status or characteristic protected by federal, state, and/or local laws. We are committed to providing reasonable accommodations for individuals with disabilities and disabled veterans in our job application procedures and in employment. If you need assistance or an accommodation due to a disability, contact us at careers@pnnl.gov . Drug Free Workplace PNNL is committed to a drug-free workplace supported by Workplace Substance Abuse Program (WSAP) and complies with federal laws prohibiting the possession and use of illegal drugs. If you are offered employment at PNNL, you must pass a drug test prior to commencing employment. PNNL complies with federal law regarding illegal drug use. Under federal law, marijuana remains an illegal drug. If you test positive for any illegal controlled substance, including marijuana, your offer of employment will be withdrawn. Security, Credentialing, and Eligibility Requirements As a national laboratory, PNNL is responsible for adhering to the Homeland Security Presidential Directive 12 (HSPD-12) and Department of Energy (DOE) Order 473.1A, which require new employees to obtain and maintain a HSPD-12 Personal Identify Verification (PIV) Credential. To obtain this credential, new employees must successfully complete the applicable tier of federal background investigation post hire and receive a favorable federal adjudication. The tier of federal background investigation will be determined by job duties and national security or public trust responsibilities associated with the job. All tiers of investigation include a declaration of illegal drug activities, including use, supply, possession, or manufacture within the last 1 to 7 years (depending on the applicable tier of investigation). Illegal drug activities include marijuana and cannabis derivatives, which are still considered illegal under federal law, regardless of state laws. For foreign national candidates: If you have not resided in the U.S. for three consecutive years, you are not eligible for the PIV credential and instead will need to obtain a favorable Local Site Specific Only (LSSO) Federal risk determination to maintain employment. Once you meet the three-year residency requirement thereafter, you will be required to obtain a PIV credential to maintain employment. The tier of federal background investigation required to obtain the PIV credential will be determined by job duties at the time you become eligible for the PIV credential. Mandatory Requirements Please be aware that the Department of Energy (DOE) prohibits DOE employees and contractors from having any affiliation with the foreign government of a country DOE has identified as a “country of risk” without explicit approval by DOE and Battelle. If you are offered a position at PNNL and currently have any affiliation with the government of one of these countries, you will be required to disclose this information and recuse yourself of that affiliation or receive approval from DOE and Battelle prior to your first day of e
Qualifications
Minimum Qualifications: Candidates must have received a PhD within the past five years (60 months) or within the next 8 months from an accredited college or university. Preferred Qualifications: PhD in computer engineering or electrical engineering. Electronic design automation (EDA) and hardware synthesis methodologies. High-level synthesis (HLS) and hardware/software co-design. Compiler infrastructures and intermediate representations, particularly the LLVM and MLIR compiler infrastructures Hardware description languages such as Verilog, SystemVerilog, or VHDL. RTL simulation, synthesis, verification, and performance analysis. Field-programmable gate array (FPGA) design and prototyping. Application-specific integrated circuit (ASIC) design flows and semiconductor tapeout. Physical design and layout tools using open-source and/or commercial EDA toolchains. Hands-on experience working with electronics in a laboratory environment, including hardware prototyping, test and measurement equipment, system bring-up, or hardware debugging. Open-source EDA technologies such as Yosys, Verilator, OpenROAD, or related tools. Commercial FPGA or ASIC design environments. Design-space exploration and optimization techniques. Artificial intelligence and machine learning (AI/ML) techniques applied to compilers, architecture, or electronic design automation. Computer architecture, domain-specific accelerators, heterogeneous computing, or chiplet-based systems. Experience working with semiconductor process design kits (PDKs), standard-cell libraries, or hardware intellectual property (IP). Development of substantial research software using languages such as C++, Python, or related systems-programming languages. Experience with collaborative software development, version control, automated testing, and reproducible research workflows.
Compensation
Minimum Salary USD $69,000.00/Yr. Maximum Salary USD $119,100.00/Yr.